module Pc (
    npc,clk,rst,pc
);
    output reg [31:0] pc;
    input [31:0] npc;
    input clk;
    input rst;
    parameter default_pc = 32'h00400000;
    initial begin
        pc <= default_pc;
            
    end
    always @(posedge clk or posedge rst) begin
        if(clk)
            pc <= npc;
        else
        begin
             pc <= default_pc; 
             $display("reset");
        end
               
    end
endmodule //pc